integrated circuit systems, inc. general description features ics9212-13 0272e?04/09/03 block diagram direct rambus? clock generator pin configuration the ics9212-13 is a high-speed clock generator providing up to 600 mhz differential clock source for direct rambus ? memory system. it includes ddll (distributed delay locked loop) and phase detection mechanism to synchronize the direct rambus ? channel clock to an external system clock. ics9212-13 provides a solution for a broad range of direct rambus memory applications. the device works in conjunction with the ics9250-09. the ics9212-13 power management support system turns ?off? the rambus ? channel clock to minimize power consumption for mobile and other power?sensitive applications. in ?clock off? mode the device remains ?on? while the output is disabled, allowing fast transitions between clock-off and clock?on states. in ?power down? mode it completely powers down for minimum power dissipation. the ics9212-13 meets the requirements for input frequency tracking when the input frequency clock is using spread spectrum clocking and also the optimum bandwidth is maintained while attenuating the jitter of the reference signal. 24-pin 150 mil ssop compatible with all direct rambus? based ic s up to 600 mhz differential clock source for direct rambus? memory system cycle to cycle jitter is less than 40ps 3.3 + 5% supply synchronization flexibility: supports systems that need clock domains of rambus channel to synchronize with system or processor clock, or systems that do not require synchronization of the rambus clock to another system clock excellent power management support refclk input is from the ics9250-09. busclk_stop# pll phase aligner pclk/m multi(0:1) synclk/n pd# fs(0:1) refclk test mux bypass mux bypclk pllclk gnd gnd 2 paclk busclkt busclkc b a phase detector vddref refclk vdd1 gnd1 gnd3 pclk/m synclk/n gnd2 vdd2 vddpd busclk_stop# pd# fs0 fs1 vdd-out gnd-out busclkt n/c busclkc gnd-out vdd-out multi0 multi1 fs2 ics9212-13 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
2 ics9212-13 0272e?04/09/03 pin descriptions pin # name type description 1 vddref refv reference voltage for refclk, to be connected to ck133 2 refclk in reference clock, to be connected to ck133 3 vdd1 pwr 3.3 v power supply used for pll 4 gnd1 pwr ground for pll 5 gnd3 pwr ground for control inputs 6,7 pclk/m, synclk/n in phase controller input, used to drive a phase aligner that adjusts the phase of the busclk. 8 gnd2 pwr ground for phase aligner 9 vdd2 pwr 3.3 v power supply used for phase aligner 10 vddpd refv reference voltage for phase detector inputs connected to the controller 11 busclk_ stop# in active low output enable/disable 12 pd# in 3.3v cmos active low power down, the device is powered down when the "(pd#) =0" 14,15 multi (0:1) in 3.3v cmos pll multiplier select, logic for selecting the multiply ratio for the pll from the input refclk 16 vdd_out pwr 3.3v supply for clock out puts 17 gnd_out pwr ground for clock outputs 18 busclkc out out put clock connected to the rambus channel. this output is the complement of busclk 19 n/c n/c not used 20 busclkt out output clock connected to the rambus channel. this output is the true component of busclk 21 gnd_out pwr ground for clock outputs 22 vdd_out pwr 3.3v supply for clock out puts 13,23,24 fs(0:2) in 3.3v cmos mode control, used in selecting bypass, test, normal, and output test (oe)
3 ics9212-13 0272e?04/09/03 multo mult1 a b pllclk for refclk=50mhz pllclk for refclk=66.66mhz 0041 reserved 266.6 0161 300 400.0 1 0 16 3 266.7 355.5 1181 400 533.3 pll divider selection and pll values (pllclk = refclk*a/b) power management modes state pwrdnb stopb normal 1 1 clk off 1 0 powerdown 0 x mode fs0 fs1 fs2 bypclk (int.) busclk busclkb normal 0 0 0 gnd paclk paclkb bypass 1 0 0 pllclk pllclk pllclkb test 1 1 0 refclk refclk refclkb vendor test a 0 0 1 - - - vendor test b 1 0 1 - - - reserved 111- - - output test (oe) 0 1 x - hi-z hi-z bypass and test mode selection
4 ics9212-13 0272e?04/09/03 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. parameters s y mbol min max uni t supply voltage vdd 3.135 3.465 v refclk input cycle time t cycle, i n 10 40 ns input cycle-to-cycle jitter t j,in -250ps input duty cycle over 10k cycles dc in 40% 60% t cycle input frequency of modulation f m, in 30 33 khz modulation index p m,in 0.25 0.5 % phase detector in p ut c y cle time at pdclk/m & s y nclk/n t cycle, pd 30 100 ns initial phase error at phase detector inputs t err,init -0.5 0.5 t cycle,pd phase detector input duty cycle over 10k cycles d cin,pd 25% 75% t cycle,pd input rise & fall times ( measured at 20%-80% of input voltage) for pdclk/m & synclk/n , &refclk t ir ,t if -1ns input capacitance at pdclk/m,synclk/n,&refclk c in,pd -7pf input capacitance matching at pclk/m & synclk/n dc in , pd -0.5pf input capacitance at cmos pins c in,cmos -10pf input (cmos) signal low voltage v il -0.3vdd input (cmos) signal high voltage v ih 0.7 - vdd refclk input low voltage v il,r - 0.3 vddi,r refclk input high voltage v ih,r 0.7 - vddi,r input signal low voltage for pd inputs and stop v il , pd - 0.3 vddi,pd input signal high voltage for pd inputs and stop v ih,pd 0.7 - vddi,pd input supply referance for refclk v dd, i r 1.3 3.465 v input supply referance vfor pd inputs v ddi ,pd 1.3 3.465 v phase detector phase error for distributed loop measured at pdclk/m & synclk/n(rising t err, pd -100 100 ps cycle cycle time t cycle 2.5 3.75 ns cycle-to-cycle jitter at busclk/busclkb (533 mhz) t j -40ps total jitter over 1 - 6 cycles (533mhz) t j -30ps phase aligner, phase step size (bsclk/busclkb) t step 1-ps pll out put phase error when tracking ssc t err,ssc -100 100 ps out put crossing-point voltage v x 1.3 1.8 v output voltage swing v cos 0.4 0.6 v output high voltage v h -2v out put duty cycle over 10k cycle dc 40% 60% t cycle output cycle -to-cycle duty cycle error t dc , er r -50ps output rise & fall times ( measured at 20%-80% of output voltage) t cr ,t cf 300 500 psd difference between rise and fall times on a single device(20%-80%) t cr, cf -100ps opearting supply current i dd 150 ma electrical characteristics-input/supply/outputs
5 ics9212-13 0272e?04/09/03 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. connections to vdd: capacitor values: c3 : 100pf ceramic all unmarked capacitors are 0.01f ceramic recommended layout
6 ics9212-13 0272e?04/09/03 150 mil ssop package l o b m y s n o m m o c s n o i s n e m i d s n o i t a i r a vds . n i m. m o n. x a m. n i m. m o n. x a m. n i m. m o n. x a mn a1 6 0 .4 6 0 .8 6 0 .a a9 8 1 .4 9 1 .6 9 1 .0 2 0 0 .5 4 0 0 .6 7 0 0 .6 1 1 a4 0 0 .6 0 0 .8 9 0 0 .b a7 3 3 .2 4 3 .4 4 3 .0 0 5 0 .5 2 5 0 .0 5 5 0 .0 2 2 a5 5 0 .8 5 0 .1 6 0 .c a7 3 3 .2 4 3 .4 4 3 .0 5 2 0 .5 7 2 0 .0 0 3 0 .4 2 b8 0 0 .0 1 0 .2 1 0 .d a6 8 3 .1 9 3 .3 9 3 .0 5 2 0 .0 8 2 0 .0 0 3 0 .8 2 c5 7 0 0 .8 0 0 .8 9 0 0 . ds n o i t a i r a v e e s e0 5 1 .5 5 1 .7 5 1 . ec s b 5 2 0 . h0 3 2 .6 3 2 .4 4 2 . l0 1 0 .3 1 0 .6 1 0 . ns n o i t a i r a v e e s ss n o i t a i r a v e e s 0 5 8 x5 8 . 03 9 . 00 0 1 . diminisions are in inches ordering information ics9212 y f-13lf example: designation for tape and reel packaging lead free (if required) pattern number (2 or 3 digit number for parts with rom code patterns) package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device ics xxxx y f - pplf t
document search | package search | parametric search | cross reference search | green & rohs | calculators | thermal data | reliability & quality | military global sites email | print contact idt | investors | press search entire site home > products > timing solutions > clock generation > general purpose ic frequency synthesizers > differential i/o > 9212-13 a dd to m y idt [ ? ] 9212-13 (differential i/o) description direct rambus? clock generator market group pc clock additional info the ics9212-13 is a high-speed clock generator providing up to 600 mhz differential cl ock source for direct rambus? memory syst em. it includes ddll (distributed delay locked loop) and phas e detection mechanism to synchronize the direct rambus? channel clock to an extern al system clock. ics9212-13 provides a solution for a broad range of direct rambus memory applications. th e device works in conjunction w ith the ics9250-09. you may also like... related orderable parts attributes 9212af-13 9212af-13lf 9212af-13lf-i n0 9212af-13lft 9212af-13lft-in0 9212af-13t voltage 3.3 v (pc24) 3.3 v (pcg24) 3.3 v (pcg24) 3.3 v (pcg24) 3.3 v (pcg24) 3.3 v (pc24) package qsop 24 qsop 24 qsop 24 qsop 24 qsop 24 qsop 24 speed na na na na na na temperature c c c c c c status active active active active active active sample yes yes yes no no no minimum order quantity 165 165 165 2500 2500 2500 factory order increment 55 55 55 2500 2500 2500 related documents type title size revision date datasheet 9212-13 datasheet 139 kb 03/23/2006 pa g e 1 of 2 08-jun-2007 mhtml:file://c:\9212-13.mh t
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